IJAIEM

International journal of application or innovation in engineering
and management
ISSN:2319-4847

Abstract

Optimized ASIC Architecture for Smart Healthcare Systems

G.Venkateswarulu, S.Mahaboob Jan , G.Tharani , S.Karthik, M.Sai Kumar Naik , P.Kartheek

Abstract

This paper presents an Application-Specific Integrated Circuit (ASIC) implementation suitable for healthcare applications that employ RISC-V as a digital processing unit and sensor interfacing circuits. Systems on Chip (SoC) are used as monitoring tools for well-being or precautionary. Healthcare system with ultra-low-power System on Chip (SoC) architecture specifically for wearable healthcare systems, in order to reduce the power consumption of the processor, designing an ASIC that handles signal processing and provides computation. The design consists of two sensors for collecting the force/pressure and ECG signal data. The RTL-based design of a processor is implemented using Verilog HDL. Logic Equivalence is verified using Xilinx ISE. Physical realizations of the design are obtained using RTL to GDSII design flow. The analog design consists of a Unity Gain Buffer, sample and holds circuit, and flash-type ADC. We have tested ASICs with AMS verification methodology using Caden

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UPDATES

  • call for paper:
    volume8
  • issue-1 october 2024
  • Submission date:
    22.10.2024

  • publishing date:28.10.2024

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