IJAIEM

Dr. C. Aruna Bala, P. Vani2, B. Anitha, K. Thrisha, K. Arun Teja, M. Harish

Abstract

Energy shortages pose a significant challenge in many developing countries, driving the need for energy-efficient digital circuits. This study presents the design and implementation of a low-power 4-bit full adder using multiple FPGA families, specifically Spartan-7 and Zynq, within the Xilinx Vivado framework. The proposed design integrates power-efficient techniques such as power gating, clock gating, and voltage scaling to minimize energy consumption while maintaining high performance. Special emphasis is placed on analyzing temperature effects, power dissipation, and overall circuit efficiency to enhance reliability and sustainability. Through extensive simulations and hardware implementation, the study demonstrates the viability of energy-conscious FPGA-based arithmetic circuits for modern communication systems. The results indicate substantial energy savings, reinforcing the importance of optimizing hardware utilization in digital design. This research contributes to the