IJAIEM

Mr. S. Shabbir Ali, G. V. Akshaya, G. Akkamma, S. Omkar, M. Brunda, B. Bharath Kumar

Abstract

This paper presents a novel block cipher architecture that integrates S-box and P-box structures to enhance encryption security and efficiency. Implemented using the Verilog hardware description language, the design is synthesized and evaluated on the Xilinx Vivado FPGA platform. The S-box and P-box components, which play a crucial role in ensuring strong cryptographic properties, are carefully optimized to achieve a balance between security and hardware efficiency. The proposed architecture is analyzed in terms of design methodology, implementation details, and performance metrics, including resource utilization and encryption strength. Experimental results demonstrate that the cipher achieves high security while maintaining efficient FPGA resource consumption. The findings underscore its potential for real-world applications requiring secure data encryption. This work contributes to the field of hardware-based cryptography by providing an optimized and scalable block cipher