IJAIEM

Gangisetti Preethi, Dr.B. Shravan Kumar

Abstract

A fault-tolerant 64×16 Random Access Memory (RAM) architecture has been designed and validated using Verilog HDL, supported by a comprehensive System Verilog-based verification environment. The system incorporates both Error Correction Code (ECC) and Built-In Self-Test (BIST) mechanisms to increase reliability and maintain data integrity in environments susceptible to transient and permanent faults—making it suitable for safety-critical and high-dependability applications.